1. Field of the Invention
The present invention relates to a digital PLL (phase-locked loop) circuit, and more particularly to a digital PLL circuit suitable for a receiver which receives a data signal in bursts including duty fluctuations and jitters.
2. Description of the Related Art
A typical PLL circuit uses a low-pass filter (LPF) to remove high frequency components from an error signal generated by a phase comparator. The oscillation frequency of a VCO (voltage-controlled oscillator) is controlled with the smoothed error signal to tune its output frequency to the input data. In the case where such a PLL circuit is applied to a burst-like digital data signal varying in phase due to frequency deviation, duty fluctuation, a jitter and so forth, the PLL circuit needs a long phase tuning time and further brings about errors when retiming the received data on the basis of a separate clock.
To solve the above problem, Baba, one of the present inventors, Invented a new digital PLL circuit and made a Japanese patent application on Mar. 1. 1995 (Japanese Patent Application No. 7-41132). The United States Patent was obtained for the same (U.S. Pat. No. 5,687,203). The digital PLL circuit is provided with a data sampling circuit which samples input data in response to N phase clocks in the direction of (received) time. The phase of the clock corresponding to, among the sampled data, the data in which edges are evenly
detected is used as a first phase or reference clock. The N phase sampled data signals are rearranged in synchronism with the first phase clock to thereby generate N phase rearranged data signals from which an optimal sampled data signal is selected. The digital PLL circuit can cope with frequency deviation, duty fluctuation, a jitter and so forth.
However, in the case of fluctuation or deviation of 50% or more, there may be cases where an identification point at which the input data is identified is erroneously determined, leading to an error when retiming the input data.